1. Field of the Invention
The present invention relates generally to electronic circuitry and, more particularly, to a method and apparatus for comparing signal propagation delay across one circuit path with signal propagation delay across another circuit path.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor. Not only does the microprocessor access a memory device to retrieve the program instructions, it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particular function. For instance, volatile memories, such as dynamic random access memories (DRAMs), must be continually powered in order to retain their contents, but they tend to provide greater storage capability and programming options and cycles than non-volatile memories, such as read only memories (ROMs).
Each memory element in a DRAM, for instance, is paired with an access device to form a memory cell. A plurality of these memory cells are typically arranged in an array of rows and columns that are addressable by the microprocessor. Most advantageously, a memory cell resides within a memory array in such a way that information can be written to it or read from it without disturbing the other cells in the array. In the case of an exemplary DRAM, a small capacitor is coupled to an access transistor. The access transistor is coupled to a row line and a column line of the array so that it can be selectively turned on or off depending upon the voltages found on the row line and the column line. When the access transistor is turned on, information in the form of a charge may be written to or read from the capacitor.
It is desirable to create memory devices that include one or more arrays of densely packed memory cells to maximize the storage capability for a given area. As the density of memory arrays increases, the cost of the memory tends to decrease while the speed of the memory tends to increase. However, as the density of a memory, or any other semiconductor device for that matter, increases, the dimensions of the individual elements which make up the semiconductor device tend to decrease. As these dimensions become increasingly smaller, it becomes more and more difficult to fabricate the elements accurately.
To gain a better understanding of these difficulties, it may be useful to discuss the manner in which integrated circuits are formed. Integrated circuits, such as memory devices, are formed by creating microscopic electronic circuits, which are typically called microelectronic circuits, on a semiconductor wafer. Once these microelectronic circuits have been fabricated on the wafer, the circuits are typically tested, and the wafer is divided into individual die, each of which contains a similar microelectronic circuit. To complete the fabrication, appropriate metal connectors are coupled to the microelectronic circuit, and a protective package is formed around the die so that the integrated circuit may be coupled to other electronic components.
During the process of fabricating a microelectronic circuit on a wafer, a process commonly referred to as a photoresist process is repeated over and over again until the microelectronic circuit has been fully fabricated. Generally speaking, a photoresist process begins with the application of a thin layer of photoresist to the surface of the wafer. Photoresist is an organic substance that, when properly developed, resists attack by acids and solvents. This layer of photoresist is developed by placing a photographic mask, which has transparent areas and opaque areas, over the wafer. When an ultraviolet light is shined through the mask, the portion of the photoresist that is exposed to the ultraviolet light either polymerizes or depolymerizes, depending upon the type of photoresist. Depolymerized portions of the photoresist may then be removed with a suitable solvent while polymerized portions of the photoresist remain on the surface of the wafer. The wafer is then typically baked to harden the remaining photoresist in preparation for remaining steps which form certain features of the microelectronic circuit. For instance, once the photoresist has been developed and baked, portions of the wafer exposed by the photoresist may be doped, etched, metalized, oxidized, or otherwise altered to fabricate certain desired aspects of the microelectronic circuit. Thereafter, the remaining photoresist is typically removed, using a mixture of inorganic acids or chemical-mechanical planarization, for instance. The process is repeated until all of the features of the microelectronic circuit have been fabricated.
It should be appreciated that fabrication processes of this type may be subject to many variations that may affect the microelectronic circuits being fabricated. Of course, as the size of such circuits becomes smaller, the effect of process variations on the circuits tends to become greater. For example, as the dimensions of a gate of a transistor become smaller, or as the gate oxide becomes thinner, the transistor tends to operate faster. Conversely, as gate dimensions become larger, or as the gate oxide becomes thicker, the transistor tends to operate slower. With circuit elements currently being fabricated with sub-micron dimensions, i.e., dimensions less than one millionth of a meter, process control becomes quite important in order to fabricate semiconductor chips which contain circuits that operate as designed.
As is clear from the above discussion, it takes a finite amount of time for each circuit element of a semiconductor circuit to perform its function. Thus, as signals propagate through sequential elements in the circuit, time delays are introduced along each signal path. A difference in time delays of signal propagation along different paths may cause a malfunction of a circuit that is typically referred to as a xe2x80x9crace.xe2x80x9d Thus, in a circuit having two or more signal propagation paths that are designed to coordinate to produce a desired function, the circuit may malfunction depending on which path of gates works faster.
The present invention may address one or more of the matters mentioned above.
Certain aspects commensurate in scope with the disclosed embodiments are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
It would be desirable to monitor the speed of certain types of circuit elements in order to determine the manner in which process variations are affecting the overall circuit. In one exemplary embodiment disclosed in detail below, a comparison circuit may be fabricated along with a primary circuit on a semiconductor substrate. The propagation delay of a comparison signal across a first path of circuit elements is compared to propagation delays of the comparison signal across a second path of delay elements. As the semiconductor fabrication process varies, the relative propagation delays across the first and second paths will vary in a manner correlative to the process variations. By monitoring the relative propagation delays, the fabrication process may be controlled to ensure that the process does not vary to an undesirable extent. Also, various programmable delay elements may be fabricated into the primary circuit, and these programmable delay elements may be activated and/or deactivated in response to the relative propagation delays of the comparison circuit.